1. Field of the Invention
The present invention relates to a vertical memory device and the method for making thereof.
2. Description of the Related Technology
With NAND Flash memory requiring higher densities and higher read/write throughput, and with traditional memory cell scaling reaching hard limits, vertical or 3D scaling approaches are being investigated. Bit-Cost Scalable (BiCS), Pipe-Shaped BiCS (P-BiCS), Terabit Cell Array Transistors (TCAT) and Dual Control-Gate with Surrounding Floating-Gate (DC-SF) appear to provide the most promising solutions to the requirement of higher densities and read/write throughput as described by H Tanaka et al., VLSI 2007, page 14, by R Katsumata et al., VLSI 2009, page 136, J Jang et al., VLSI 2009, page 192 and S Whang, IEDM 2010, page 669.
BiCS is the simplest approach, but a major drawback with this approach is the difficulty to be able to create a junction at the bottom of the memory hole. The exposed tunnel oxide is attacked during dry etch of the gate stack at the bottom and also by diluted HF (DHF) clean. DC-SF faces the same problem, and to avoid bottom junction formation, complicated pipeline construction (P-BiCS) or expensive gate replacement technology (TCAT) is required. The latter concepts are not optimal in terms of density, because of pipeline and word line separation respectively.
There is therefore a need to provide a method of constructing a vertical memory cell which solves the problem of tunnel oxide integrity.